;code uses this column

;started on: 12/05/06
;last mod:   12/09/06
;
;
;
;
 
 list         p=18F452  ;microchip's latest bastard child

w equ 0
f equ 1      ;w/f flag

a equ 0
b equ 1      ;a/b flag

n  equ 4
v  equ 3
z  equ 2
dc equ 1
c  equ 0     ;status flags


	     cblock h'80'   ;PIC registers
	     porta
	     portb
	     portc
	     portd
	     porte:5
	     lata
	     latb
	     latc
	     latd
	     late:5
	     trisa
	     trisb
	     trisc
	     trisd
	     trise:7
	     pie1
	     pir1
	     ipr1
	     pie2
	     pir2
	     ipr2:4
	     eecon1
	     eecon2
	     eedata
	     eeadr:2
	     rcsta
	     txsta
	     txreg
	     rcreg
	     spbrg:2
	     t3con
	     tmr3l
	     tmr3h:7
	     ccp2con
	     ccpr2l
	     ccpr2h
	     ccp1con
	     ccpr1lr
	     ccpr1hr:2
	     adcon1
	     adcon0
	     adresl
	     adresh
	     sspcon2
	     sspcon1
	     sspstat
	     sspadd
	     sspbuf
	     t2con
	     pr2
	     tmr2
	     t1con
	     tmr1l
	     tmr1h
	     rcon
	     wdtcon
	     lvdcon
	     osccon:2
	     t0con
	     tmr0l
	     tmr0h
	     status
	     fsr2l
	     fsr2h
	     plusw2
	     preinc2
	     postdec2
	     postinc2
	     indf2
	     bsr
	     fsr1l
	     fsr1h
	     plusw1
	     preinc1
	     postdec1
	     postinc1
	     indf1
	     wreg
	     fsr0l
	     fsr0h
	     plusw0
	     preinc0
	     postdec0
	     postinc0
	     indf0
	     intcon3
	     intcon2
	     intcon
	     prodl
	     prodh
	     tablat
	     tblptrl
	     tblptrh
	     tblptru
	     pclow
	     pclath
	     pclatu
	     stkptr
	     tosl
	     tosh
	     tosu
	     endc

	     cblock h'20'
	     temp
	     temp2
	     tmp232
	     acount0
	     acount1
	     acount2
	     rdelay
	     ctr
	     ctr0
	     ctr1
	     ctr2
	     endc
	     
	     org    h'0000'        ;Start
	     bra    start
	     
	     org    h'0008'
	     bra    otherint
	     
	     org    h'0018'
	     
	     retfie 1           ;don't use fast save

otherint:    retfie 0

start:       clrf   intcon,a
	     bcf    rcon,1,a
	     movlb  h'00'
	     movlw  h'd7'
	     movwf  lata,a  
	     clrf   latb,a
	     clrf   latc,a  
	     clrf   latd,a  
	     clrf   late,a  
	     clrf   adcon0,a      ;disable ADC
	     movlw  h'06'
	     movwf  adcon1,a      ;set up pins for digital only
	     movlw  h'35'
	     movwf  trisa,a       ;tmr0 CLK in, input
	     setf   trisb,a  
	     movlw  h'c1'
	     movwf  trisc,a       ;set up input/output ports
	     clrf   trisd,a  
	     clrf   trise,a       ;outs
	     movlw  h'f2'
	     movwf  t0con,a       ;tmr0 on ext clock, ps div by 16
	     movlw  rs232      ;<- 115.2kbps d'28' for 57.6
	     movwf  spbrg,a       ;set up brg
	     movlw  h'24'      
	     movwf  txsta,a       ;asynch, 8 bit, tx enabled, hi brg
	     movlw  h'90'
	     movwf  rcsta,a       ;final set up of serial port

	     lfsr   0,h'000'
		      
c_lp:        movf   fsr0l,w,a
	     clrf   postinc0,a
	     movlw  h'80'
	     cpfseq fsr0l,a
	     bra    c_lp        ;clear all RAM
	     
	     clrf   intcon,a      ;in case of crash, turn off ints
	     bsf    rcon,7,a       ;turn on the dual priority interrupt mode
	     movlw  h'00'   ;was 84
	     movwf  intcon2,a     ;no pullups, tmr0 assigned to hi pri
	     clrf   intcon3,a     ;disable these totally
	     movlw  h'04'
	     movwf  pie1,a        ;turn on ccp1 interrupt enable
	     clrf   pie2,a        ;disable all pie 2 ints
	     movlw  h'30'
	     movwf  ipr1,a        ;set ccp1 interrupt to hi pri
	     movlw  h'00'
	     movwf  ipr2,a        ;set tmr3 overflow to hi pri
	     clrf   pir1,a
	     clrf   pir2,a        ;clear all int flags just in case
	     
	     clrf   pclatu,a      ;clear pclatu here only
	     
	     
;start of the lockout chip code.             

;
;portA.0 = Dout from lockout chip (pin 1 of lockout chip in "lock" mode)
;portA.1 = Din to lockout chip (pin 2 of lockout chip in "lock" mode)
;portA.2 = Reset Out (pin 10 of lockout chip in "lock" mode)
;portA.3 = CLK (pin 7 of lockout chip in "lock" mode)
;
;portD.0 = LED indicating transmit / hash function
;portD.1 = LED indicating we clocked the chip once
;
;


	     lfsr   0,0h

lockstart:   bcf    lata,1,a
	     bcf    latd,0,a
	     bcf    latd,1,a
	     movlw  h'00'       ;init RAM data
	     movwf  0bh,a
	     movlw  h'01'
	     movwf  05h,a
	     movwf  0ah,a
	     movwf  0dh,a
	     movlw  h'02'
	     movwf  01h,a
	     movwf  04h,a
	     movwf  06h,a
	     movwf  0eh,a
	     movlw  h'04'
	     movwf  0fh,a
	     movlw  h'08'
	     movwf  0ch,a
	     movlw  h'09'
	     movwf  07h,a
	     movwf  09h,a
	     movlw  h'0f'
	     movwf  08h,a
	     
	     movlw  h'1f'      ;waste 21h cycles
	     call   clockit2
	     movlw  h'0c'
	     movwf  fsr0l,a
	     movlw  h'04'
	     movwf  ctr,a

	     call   clockit
	     call   clockit
	     call   clockit

seedloop:     bcf    latd,0,a
	     movlw  h'01'      ;grab the seed
	     andwf  porta,w,a
	     movwf  temp,a     ;Din
	     movf   indf0,w,a
	     btfsc  temp,0,a
	     addwf  01h,f,a
	     movf   temp,w,a
	     movwf  indf0,a
	     
	     call   clockit
	      
	      bsf    latd,0,a
	     movlw  h'0e'
	     call   clockit2
	     
	     
	     
	     incf   fsr0l,f,a
	     decfsz ctr,f,a
	     goto   seedloop


copyloop:    movlw  h'0f'    ;specific things we set up
	     andwf  01h,f,a
	     movwf  0dh,a
	     movwf  15h,a
	     movlw  h'0d'
	     movwf  0ch,a
	     movlw  h'09'
	     movwf  02h,a
	     movwf  12h,a
	     movwf  0eh,a
	     movwf  1ch,a
	     movwf  1dh,a
	     movwf  1eh,a
	     movlw  h'07'
	     movwf  0fh,a
	     movwf  1fh,a
	     movlw  h'05'
	     movwf  03h,a
	     movwf  13h,a
	     movlw  h'03'
	     movwf  11h,a
	     movlw  h'00'
	     movwf  17h,a

	     movf   04h,w,a   ;stuff we move along
	     movwf  14h,a
	     movf   06h,w,a
	     movwf  16h,a
	     movf   08h,w,a
	     movwf  18h,a
	     movf   09h,w,a
	     movwf  19h,a
	     movf   0ah,w,a
	     movwf  1ah,a
	     movf   0bh,w,a
	     movwf  1bh,a

	     movlw  h'49'         ;removed 2
	     call   clockit2

main:        
	     movlw  h'1d'
	     call   clockit2

	     movf   07h,w,a
	     addlw  h'08'
	     andlw  h'0f'
	     movwf  fsr0l,a
	     btfss  status,z,a   ;waste 2 cycles
	     goto   ml_0
	     incf   fsr0l,f,a
	     
	     movlw  h'02'
	     call   clockit2    ;waste those cycles

ml_0:        
	     

ml_1:        btfsc  porta,0,a
	     bra    fuckedup
	     
	     movlw  h'03'
	     call   clockit2
	     call   clockit
	     call   clockit
	     
	     btfsc  indf0,0,a
	     bsf    lata,1,a     ;set output bit if needed
	     call   clockit
	     movf   porta,w,a
	     call   clockit
	     
	     call   clockit
	     bcf    lata,1,a     ;then clear it
	     call   clockit
	     bsf    fsr0l,4,a
	     xorwf  indf0,w,a
	     bcf    fsr0l,4,a
	     andlw  h'01'
	     btfss  status,z,a
ml_2:        bra    fuckedup

	     movlw  h'46'
	     call   clockit2
	     incf   fsr0l,f,a
	     btfss  fsr0l,4,a
	     bra    ml_1
	     
	     btg    latd,0,a
	     movlw  h'02'
	     movwf  fsr0l,a
	     
hash:        movlw  h'0d'
	     addwf  fsr0l,f,a
	     movf   indf0,w,a
	     addlw  h'0e'
	     andlw  h'0f'
	     movwf  ctr,a
	     movlw  h'f3'
	     addwf  fsr0l,f,a   ;back to 2/12
	     
h_inner:                  

	     incf   indf0,w,a   ;1     ;(2)+1
	     incf   fsr0l,f,a   ;1     ;
	     addwf  indf0,w,a   ;1     ;(3)+(2)+1
	     movwf  temp,a      ;1
	     btfss  temp,4,a    ;1
	     bra    h_1         ;3
	     andlw  h'0f'       ;
	     nop                ;
	     nop                ;
	     nop                ;
	     bra    h_2         ;

h_1:         xorwf  indf0,w,a     ;1      ;swap wreg & 03h
	     xorwf  indf0,f,a     ;1
	     xorwf  indf0,w,a     ;1
	     incf   fsr0l,f,a   ;1

h_2:     ;    movwf  sum,a    
	 ;P = 3 or 4

	     addwf  indf0,w,a   ;sum += R[P]
	     andlw  h'0f'       
	     movwf  indf0,a     ;R[P] = sum & 0fh

	     incf   fsr0l,f,a   ;P=P+1

	     addwf  indf0,w,a   ;sum += R[P+1]
	     andlw  h'0f'

	     xorwf  indf0,w,a  ;tmp = R[P+1]
	     xorwf  indf0,f,a  ;R[P+1] = sum & 0fh
	     xorwf  indf0,w,a  ;swap R[P+1] w/ wreg

	     incf   fsr0l,f,a  ;P=P+1
	     
	     addlw  h'f8'      ;add 8 and check for > 10h
	     btfss  status,c,a ;yep, > 10h
	     addwf  indf0,w,a  ;nope, add R[P+2] 
	     andlw  h'0f'

	     xorwf  indf0,w,a
	     xorwf  indf0,f,a
	     xorwf  indf0,w,a  ;swap R[P+2] w/ wreg
			       ;wreg = sum
	     
	     btfss  fsr0l,0,a  ;check for 3/4
	     bra    h_3        ;4
	     incf   fsr0l,f,a  ;3, now 6
	     addwf  indf0,w,a
	     addlw  h'01'
	     andlw  h'0f'
	     movwf  indf0,a
	     nop
	     nop
	     nop
	     call   clockit    ;6 wasted cycles
	     call   clockit
	     call   clockit
	     call   clockit
	     call   clockit
	     call   clockit

h_3:         addlw  h'08'
	     
	     incf   fsr0l,f,a  ;7
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a
	     
	     incf   fsr0l,f,a  ;8
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;9
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;a
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;b
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;c
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;d
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;e
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;f
	     addwf  indf0,w,a
	     addlw  h'09'
	     andlw  h'0f'
	     movwf  indf0,a

	     movlw  h'f2'
	     addwf  fsr0l,f,a  ;1
	     incf   ctr,w,a
	     addwf  indf0,w,a
	     andlw  h'0f'
	     movwf  indf0,a

	     incf   fsr0l,f,a  ;2
	     addwf  indf0,w,a
	     xorlw  h'0f'
	     addlw  h'01'
	     andlw  h'0f'
	     movwf  indf0,a

	     movlw  h'4e'
	     call   clockit2
	     
	     decf   ctr,f,a
	     btfss  ctr,7,a
	     bra    h_inner
	     btg    fsr0l,4,a
	     btfsc  fsr0l,4,a
	     bra    hash
	     btg    latd,0,a
	     bra    main



tempdone:
	     call   clockit
	     
	     
	     
	     bra    tempdone
	     



clockit2:    bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     call   cdel
	     bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     call   cdel
	     bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     call   cdel
	     bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     call   cdel
	     btfss  porta,2,a
	     bra    ci2_x
	     pop
	     bra    lockstart

ci2_x:       decfsz wreg,f,a
	     bra    clockit2
	     return



clockit:     
	     bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bsf    lata,3,a
	     nop
	     nop
	     nop
	     nop
	     bcf    lata,3,a
	     nop
	     nop
	     nop
	     nop

	     call   cdel
	     btfss  porta,2,a
	     return
	     pop
	     bra    lockstart
	     
	     
cdel:        btg    latd,1,a
	     clrf   ctr0,a             
	     clrf   ctr1,a
	     clrf   ctr2,a

	     
cdloop:  ;    decfsz ctr0,f,a
	 ;    goto   cdloop
      ;       decf   ctr1,f,a
      ;       btfsc  ctr1,3,a
      ;       goto   cdloop
	 ;    decf   ctr2,f,a
	 ;    btfss  ctr2,1,a
	 ;    goto   cdloop
	     return


fuckedup:    call   clockit
	     goto   fuckedup
	     
	     

	     end